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19-3974; Rev 1; 4/07
KIT ATION EVALU BLE AVAILA
High-Speed, Dual-Phase Driver with Integrated Boost Diodes
General Description Features
Dual-Phase Synchronous Buck Driver Integrated Bootstrap Diodes Up to 26V System Input Voltage 6A Peak Gate Drive Current Capable of 30A per Phase 0.4/0.9 Low-Side, 0.7/1.0 High-Side Drivers (typ) Typical 11ns Rise/Fall Times with 3000pF Load Adaptive Dead-Time Control User-Programmable Delay Time Enable Function with 0.04A (typ) Quiescent Current in Shutdown Space-Saving, Lead-Free, 16-Pin QSOP
MAX8811
The MAX8811 2-phase gate driver controls power MOSFETs in multiphase synchronous step-down converter applications, providing up to 30A output current per phase. The MAX8811 and MAX8810A (multiphase power-supply controller) combine to provide an efficient, low-cost solution for a wide range of multiphase powersupply applications. The MAX8811 handles system input voltages up to 26V. Each MOSFET driver is capable of driving 3000pF capacitive loads with 11ns typical rise and fall times. Adaptive shoot-through protection circuitry is implemented to prevent shoot-through currents for the "highside off to low-side on" transition. A programmable delay is provided for the "low-side off to high-side on" transition. This maximizes overall converter efficiency while supporting operation with a variety of MOSFETs. The MAX8811 provides an easy upgrade path from the MAX8523 dual driver. Integrated bootstrap diodes reduce external component count, while an enable input provides flexibility for power sequencing. The MAX8811 is available in a space-saving, 16-pin QSOP.
Ordering Information
PART MAX8811EEE+ TEMP RANGE -40C to +85C PINPACKAGE 16 QSOP PKG CODE E16-4
Applications
Processor Core Voltage Regulators Multiphase Buck Converters Voltage-Regulator Modules (VRMs) Switching Power Supplies DC-DC Converter Modules
+Denotes a lead-free package.
Pin Configuration
Typical Operating Circuit
GATE-DRIVE SUPPLY 4.5V TO 7V 4 POWER INPUT UP TO 26V VL1 VL2 DH1 BST1 LX1 DL1 8 DLY PGND1 2 1 3 5 6 OUTPUT +
TOP VIEW
BST1 1 DH1 2 LX1 3 VL1 4 DL1 5 PGND1 6 EN 7 DLY 8 + 16 BST2 15 DH2 14 LX2
13
MAX8811
13 VL2 12 DL2 11 PGND2 10 PWM2
OFF ON
MAX8811
DH2 7 9 EN PWM1 BST2 LX2 DL2 PGND2 15 16 14 12 11
9
PWM1
QSOP
PWM CONTROL SIGNALS
10 PWM2
________________________________________________________________ Maxim Integrated Products
1
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High-Speed, Dual-Phase Driver with Integrated Boost Diodes MAX8811
ABSOLUTE MAXIMUM RATINGS
DLY, EN, PWM_, DL_ to PGND_.................-0.3V to (VVL_+ 0.3V) BST_ to PGND_ ............................................-0.3V to (VLX_ + 8V) BST_ to VL_ ...............................................................-1V to +30V LX_ to PGND_............................................................-1V to +28V DH_ to PGND_.........................................-0.3V to (VBST_ + 0.3V) DH_, BST_ to LX_ .....................................................-0.3V to +8V VL_ to PGND_ ..........................................................-0.3V to +8V DH_, DL_ Current ................................................. 200mA RMS VL_ to BST_ Internal Diode Current .........................50mA RMS PGND1 to PGND2 .................................................-0.3V to +0.3V Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8.3 mW/C above +70C)......666.7 mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDLY = VEN = VBST_ = VVL_ = 6.5V, VPGND_ = VLX_ = VPWM_ = 0V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER GENERAL VL_ Input Voltage Range LX Operating Range VL_ Undervoltage Lockout (UVLO) Supply Current (per Channel) IBST_ + IVL_ Shutdown Supply Current (per Channel) IBST_ + IVL_ PWM_ Input Leakage Input Voltage High Threshold Input Voltage Low Threshold Input Threshold Hysteresis EN Input Leakage Input Voltage High Threshold Input Voltage Low Threshold Input Voltage Hysteresis DLY Delay Disable Threshold VVL_ - VDLY 0.8 1.2 V 0.8 0.5 VPWM_ = 0V or 7.0V, VEN = 0V or 7.0V 0.01 2.6 A V V V 1.2 20 VPWM_ = 0V or 7.0V, VEN = 0V or 7.0V 0.01 3.5 A V V % VVL_ rising, 250mV hysteresis (typ) VPWM__= 0V VPWM__ = VDLY = VVL_ VEN = 0V, VPWM_ = 0V or VVL_ 3.25 0.7 1.4 0.04 4.5 7 26 3.8 1.5 2 1 V V V mA A CONDITIONS MIN TYP MAX UNITS
2
_______________________________________________________________________________________
High-Speed, Dual-Phase Driver with Integrated Boost Diodes
ELECTRICAL CHARACTERISTICS (continued)
(VDLY = VEN = VBST_ = VVL_ = 6.5V, VPGND_ = VLX_ = VPWM_ = 0V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER GATE DRIVER SPECIFICATIONS VPWM_ = VVL_, sourcing current DH_ Driver Resistance VPWM_ = 0V, sinking current VPWM_ = 0V, sourcing current DL_ Driver Resistance VPWM_ = VVL_, sinking current DH_ Rise Time (trDH) DH_ Fall Time (tfDH) DL_ Rise Time (trDL) DL_ Fall Time (tfDL) VPWM_ = VVL_ VPWM_ = 0V VPWM_ = 0V VPWM_ = VVL_ VPWM_ falling (tpDHf) VPWM_ = VVL _ , VDL _ falling (tpDHr) VPWM_ rising (tpDLf) VPWM_ = GND, LX falling (tpDLr) INTERNAL BOOST DIODE SPECIFICATIONS On-Resistance THERMAL SHUTDOWN Thermal Shutdown Rising temperature, hysteresis = 15C (typ) +165 C IBST_ = 40mA 6 VVL_= 6.5V, IDL_= 0.1A VBST_ = 6.5V, 3000pF load VBST_ = 6.5V, 3000pF load VVL_ = 6.5V, 3000pF load VVL_ = 6.5V, 3000pF load 0.4 14 9 11 8 20 VBST_ = 6.5V 14 12 VBST_ - VLX_ = 6.5V 16 ns ns 0.7 ns ns ns ns VBST_ = 6.5V, IDH_ = 0.1A VVL_ = 6.5V, IDL_= -0.1A 0.7 0.9 1.1 1.5 VBST_ = 6.5V, IDH_ = -0.1A 1.0 1.6 CONDITIONS MIN TYP MAX UNITS
MAX8811
DH_ Propagation Delay
DL_ Propagation Delay
Note 1: Specifications at -40C guaranteed by design.
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3
High-Speed, Dual-Phase Driver with Integrated Boost Diodes MAX8811
Typical Operating Characteristics
(VVL1 = VVL2 = VEN = VDLY = 6.5V, 3000pF capacitive load, TA = +25C, unless otherwise noted.)
VL_ POWER DISSIPATION vs. LOAD CAPACITANCE
MAX8811toc02
VL_ POWER DISSIPATION vs. PER-PHASE SWITCHING FREQUENCY
MAX8811toc01
DL RISE/FALL vs. LOAD CAPACITANCE
MAX8811toc03
700 VL_ POWER DISSIPATION (mW) 600 500 400 300 200 100 0 0 200 400 600 800
400 350 VL_ POWER DISSIPATION (mW) 300 250 200 150 100 50 0 fSW = 200kHz 1000 3000 5000
30 25 RISE/FALL TIME (ns) 20 DL RISE 15 10 5 0 1000 3000 fSW = 200kHz 5000 DL
1000
7000
7000
fS (kHz)
DH/DL LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
DH RISE/FALL TIME vs. LOAD CAPACITANCE
MAX8811toc04
RISE AND FALL TIMES vs. TEMPERTURE
MAX8811toc05
VL_ SUPPLY CURRENT vs. PER-PHASE SWITCHING FREQUENCY
MAX8811toc06
30 25 RISE/FALL TIME (ns) 20 DH RISE 15 DH FALL 10 5 0 0 2000 4000 6000
16 14 12 TIME (ns) 10 8 6 4 2 3000pF LOAD 0 DH FALL DL FALL DH RISE DL RISE
120 100 80 60 40 20 0
VL_ SUPPLY CURRENT (mA)
8000
-40
-15
10
35
60
85
0
200
400
600
800
1000
LOAD CAPACITANCE (pF)
TEMPERATURE (C)
fS (kHz)
PROPAGATION DELAY vs. TEMPERATURE
MAX8811toc07
PROGRAMMABLE DELAY vs. RDLY
MAX8811toc11
25 tpDHf 20 tpDLr
120 100 80 60 40 20 0
TIME (ns)
15 tpDHr 10 tpDLf 5
0 -40 -15 10 35 60 85 TEMPERATURE (C)
DELAY (ns)
0
10 20 30 40 50 60 70 80 90 100 RDLY (k)
4
_______________________________________________________________________________________
High-Speed, Dual-Phase Driver with Integrated Boost Diodes
Typical Operating Characteristics (continued)
(VVL1 = VVL2 = VEN = VDLY = 6.5V, 3000pF capacitive load, TA = +25C, unless otherwise noted.)
SWITCHING WAVEFORMS
MAX8811toc09
MAX8811
VBST_ AND VL_ WAVEFORMS
MAX8811toc10
VPWM 5V/div
VL (AC-COUPLED) 500mV/div
VLX 10V/div VDL 5V/div
VBST (AC-COUPLED) 200mV/div
VDH 5V/div 100ns/div
fSW = 250kHz 1s/div
VLX 10div
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME BST1 DH1 LX1 VL1 DL1 PGND1 EN DLY PWM1 PWM2 PGND2 DL2 VL2 LX2 DH2 BST2 FUNCTION Boost Capacitor Connection for Phase 1. Connect a 0.22F ceramic capacitor between BST1 and LX1. High-Side Gate-Driver Output for Phase 1. DH1 is pulled low during shutdown and UVLO. Inductor Connection for Phase 1 Gate-Drive Supply for DL1. Connect VL1 to a 4.5V to 7V supply. VL1 must be connected to VL2 externally. Bypass the VL1/VL2 connection with a 2.2F or larger ceramic capacitor to the power ground plane. Low-Side Gate-Driver Output for Phase 1. DL1 is pulled low during shutdown and UVLO. Power Ground for DL1. Connect PGND1 and PGND2 to the power ground plane at the IC. Enable Input. Drive EN high for normal operation, or low for shutdown. Delay Time Setting Input. Connect a resistor from DLY to PGND1 to set the dead time between DL falling and DH rising, or connect DLY to VL1 to use the default delay. PWM Logic Input for Phase 1. DH1 is high when PWM1 is high; DL1 is high when PWM1 is low. PWM Logic Input for Phase 2. DH2 is high when PWM2 is high; DL2 is high when PWM2 is low. Power Ground for DL2. Connect PGND1 and PGND2 to the power ground plane at the IC. Low-Side Gate-Driver Output for Phase 2. DL2 is pulled low during shutdown and UVLO. Gate-Drive Supply for DL2. Connect VL2 to a 4.5V to 7V supply. VL1 must be connected to VL2 externally. Bypass the VL1/VL2 connection with a 2.2F or larger ceramic capacitor to the power ground plane. Inductor Connection for Phase 2 High-Side Gate-Driver Output for Phase 2. DH2 is pulled low during shutdown and UVLO. Boost Capacitor Connection for Phase 2. Connect a 0.22F ceramic capacitor between BST2 and LX2.
_______________________________________________________________________________________
5
High-Speed, Dual-Phase Driver with Integrated Boost Diodes MAX8811
BST1 DH1 LX1 VL1 DL1 PGND1 PHASE 1 EN VL1 VL2 PWM2 EN LOGIC UVLO LX1 LOW DETECT
DHON DHLO DLON DLLO PWM1
MAX8811
DHON DHLO DLON DLLO BST2 DH2 LX2 VL2 DL2 PGND2
PHASE 2
LX2 LOW DETECT
Figure 1. Functional Diagram
tpDLf
tpDHf
PWM DL tfDL tpDHr (tDLY)* tpDLr trDL
LX trDH tfDH
DH *WHEN RDLY IS USED, tpDHr BECOMES THE USER-PROGRAMMABLE TIME DELAY, tDLY. DRAWING IS NOT TO SCALE.
Figure 2. Driver Timing Diagram
6
_______________________________________________________________________________________
High-Speed, Dual-Phase Driver with Integrated Boost Diodes
Detailed Description
Principles of Operation
MOSFET Gate Drivers (DH_, DL_) DH_ is driven high when the PWM_ is high; DL_ is driven high when PWM_ is low. PWM pulsewidths under 20ns (typ) are rejected, and no switching occurs. The low-side drivers (DL_) have typical 0.9 sourcing resistance and 0.4 sinking resistance, and are capable of driving 3000pF capacitive loads with 11ns typical rise and 8ns typical fall times. The high-side drivers (DH_) have typical 1.0 sourcing resistance and 0.7 sinking resistance, and are capable of driving 3000pF capacitive loads with 14ns typical rise and 9ns typical fall times. This facilitates fast switching, reducing switching losses, and makes the MAX8811 ideal for both high-frequency and high-output current applications. Shoot-Through Protection Adaptive shoot-through protection is incorporated for the switching transition after the high-side MOSFET is turned off and before the low-side MOSFET is turned on. The low-side driver is turned on when the LX voltage falls below 2.5V, or after 135ns typical delay, whichever occurs first. Furthermore, the delay time between the low-side MOSFET turn-off and high-side MOSFET turn-on can be adjusted by selecting the value of R1 (see the Setting the Dead Time section).
Table 1. Components for Figure 3, 800kHz, 20A/Phase Typical Application Circuit
DESIGNATION C1 DESCRIPTION 2 x 10F 20%, X7R 25V capacitor 12103D106MAT2W 2 x 10F 20%, X7R 25V capacitor 12103D106MAT2W 2.2F 20%, 10V X5R capacitor GRM39X5R225K10 0.22F 20%, 10V X7R capacitors GRM39X7R224K10 100F 20%, 6.3V X5R capacitors C3225X5R0J107M 0.2H, 28A inductors FDV0630R20M,1.9m DCR HAT2168, 8m, 30V MOSFET 2 x HAT2164H, 3m, 30V, MOSFET 2 x HAT2164H, 3m, 30V MOSFET Dead-time delay programming resistor; see Programmable Delay vs. RDLY in the Typical Operating Characteristics MANUFACTURER AVX
MAX8811
C2
AVX
C3
Murata
C4, C5
Murata
C6-C9
TDK
L1, L2
TOKO
Q1, Q3 Q2 Q4
Renesas Renesas Renesas
Undervoltage Lockout (UVLO)
When the voltage at the VL1/VL2 connection is below the UVLO threshold, all driver outputs are held low. This prevents switching when the supply voltage is too low for proper operation.
R1
--
Thermal Protection
Thermal-overload protection limits total power dissipation in the MAX8811. When the junction temperature exceeds +165C, all driver outputs are held low. The IC resumes normal operation after the junction temperature cools by 15C (typ).
Boost Capacitor Selection
The MAX8811 uses a bootstrap circuit to generate the supply voltages for the high-side drivers (DH_). The selected high-side MOSFET determines the appropriate boost capacitance values, according to the following equation: CBST = QGATE VBST
where QGATE is the total gate charge of the high-side MOSFET and VBST is the voltage variation allowed on the high-side MOSFET drive. Choose VBST = 0.1V to 0.2V when determining CBST. Low-ESR ceramic capacitors should be used.
VL_ Decoupling
VL1 and VL2 provide the supply voltage for the low-side drivers. The decoupling capacitors at VL_ also charge the BST capacitors during the time period when DL_ is high. Therefore, the decoupling capacitor C3 for VL_ should be large enough to minimize the ripple voltage during switching transitions. Choose the VL capacitor approximately 10 times the value of the BST capacitor value.
_______________________________________________________________________________________
7
High-Speed, Dual-Phase Driver with Integrated Boost Diodes MAX8811
Table 2. Components for Figure 4, 300kHz, 30A/Phase Typical Application Circuit
DESIGNATION C1 DESCRIPTION 2 x 10F 20%, X7R 25V capacitor 12103D106MAT2W 2 x 10F 20%, X7R 25V capacitor 12103D106MAT2W 2.2F 20%, 10V X5R capacitor GRM39X5R225K10 0.22F 20%, 10V X7R capacitors GRM39X7R224K10 2700F 20%, 6.3V capacitors MFZ series, 7m max ESR T50183, 250nH inductors at 35A 20%, 0.68m DCR 2 x HAT2168, 8m, 30V MOSFET 2 x HAT2164H, 3m, 30V MOSFET 2 x HAT2168, 8m, 30V MOSFET 2 x HAT2164H, 3m, 30V MOSFET MANUFACTURER AVX
Avoiding dV/dt-Induced Low-Side MOSFET Turn-On
At high input voltages, fast turn-on of the high-side MOSFET could momentarily turn on the low-side MOSFET due to the high dV/dt appearing at the drain of the low-side MOSFET. The high dV/dt causes a current flow through the Miller capacitance (CRSS) and the input capacitance (CISS) of the low-side MOSFET. Improper selection of the low-side MOSFET that has a high ratio of CRSS/CISS makes the problem more severe. To avoid the problem, give special attention to the ratio of C RSS /C ISS when selecting the low-side MOSFET. Adding a resistor between BST_ and the BST_ capacitor slows the high-side MOSFET turn-on. Adding a capacitor from the gate to the source of the high-side MOSFET has the same effect. However, both methods are at the expense of increasing the switching losses.
C2
AVX
C3
Murata
C4, C5
Murata
Applications Information
Rubycon
C6, C7, C8
Power Dissipation
Power dissipation in the IC package comes mainly from switching the MOSFETs. Therefore, it is a function of both switching frequency and the total gate charge of the selected MOSFETs. The total power dissipation when both drivers are switching is given by:
PIC = 2 x fS x [N x QG _ TOTAL _ HS x RHS + M x QG _ TOTAL _ LS x RHS + (RG _ HS / N) RLS + RG _ LS / M
L1, L2
Falco Electronics
Q1 Q2 Q3 Q4
Renesas Renesas Renesas Renesas
(
RLS
)
] x VPV _ + VVCC x IVCC
Setting the Dead Time
Connect DLY to VL_ for the default delay time, typically 14ns. To increase the delay between the low-side MOSFET drive turn-off and the high-side MOSFET turnon, connect a resistor from DLY to PGND1. See the Typical Operating Characteristics section for a plot of the delay time vs. resistor value. The equation for this resistor is: tDLY = 14s + (1pF) x RDLY
where fS is the switching frequency, QG_TOTAL_HS is the total gate charge of the selected high-side MOSFET, Q G_TOTAL_LS is the total gate charge of the selected low-side MOSFET, N is the total number of the high-side MOSFETs in parallel, M is the total number of the low-side MOSFETs in parallel, VVL is the voltage at VL, RHS is the on-resistance of the high-side MOSFET, and RG_LS is the gate resistance of the selected lowside MOSFETs.
8
_______________________________________________________________________________________
High-Speed, Dual-Phase Driver with Integrated Boost Diodes
PCB Layout
The MAX8811 sources and sinks large currents to drive MOSFETs at high switching speeds. The high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. The following PCB layout guidelines are recommended when designing with the MAX8811: 1) Place all decoupling capacitors as close to their respective pins as possible. 2) Minimize the high-current loops from the input capacitor, upper switching MOSFET, and low-side MOSFET back to the input capacitor negative terminal. 3) Provide enough copper area at and around the switching MOSFETs and inductors to aid in thermal dissipation. 4) Connect PGND1 and PGND2 as close as possible to the source of the low-side MOSFETs. 5) Keep LX1 and LX2 away from sensitive analog components and nodes. 6) Gate drive traces should be at least 20 mils wide, kept as short as possible, and tightly coupled to reduce EMI and ringing induced by high-frequency gate noise. Adjacent DH_ and LX_ traces should be tightly coupled. A sample evaluation layout is available in the MAX8811 Evaluation Kit.
MAX8811
Chip Information
PROCESS: BiCMOS
_______________________________________________________________________________________
9
High-Speed, Dual-Phase Driver with Integrated Boost Diodes MAX8811
GATE-DRIVE SUPPLY 4.5V TO 7V VIN = 12V VL1 DH1 DLY VL2 C3 DL1 PGND1 Q2 BST1 LX1 C6 C7 C8 Q1 C4 R1 L1 VOUT C9 C1
MAX8811
ON OFF EN PWM1 PWM2 PWM CONTROL SIGNALS BST2 DH2 LX2 DL2 Q4 PGND2 Q3 C5
C2
L2
Figure 3. 800kHz, 20A/Phase Typical Application Circuit
GATE-DRIVE SUPPLY 4.5V TO 7V
VIN = 12V VL1 DH1 DLY VL2 BST1 LX1 DL1 PGND1 Q1 C4 L1 VOUT C1
C3 Q2 C6 C7 C8
MAX8811
ON OFF EN PWM1 PWM2 PWM CONTROL SIGNALS BST2 DH2 LX2 DL2 Q4 PGND2 Q3 C5
C2
L2
Figure 4. 300kHz, 30A/Phase Typical Application Circuit
10
______________________________________________________________________________________
High-Speed, Dual-Phase Driver with Integrated Boost Diodes
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX8811
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
F
1 1
Revision History
Pages changed at Rev 1: 1, 2, 7, 8, 11
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
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